# VU Cs302 – Digital Logic Design (Session – 2) FinalTerm Solved Unsolved Past Papers

** ****MIDTERM EXAMINATION**

**CS302- Digital Logic Design (Session – 2**

**Question No: 1 ( Marks: 1 ) – Please choose one**

Which of the number is not a representative of hexadecimal system

► 1234

► ABCD

► 1001

► DEFH

**Question No: 2 ( Marks: 1 ) – Please choose one**

The Unsigned Binary representation can only represent positive binary numbers

► True

► False

**Question No: 3 ( Marks: 1 ) – Please choose one**

The values that exceed the specified range can not be correctly represented and are considered as

________

► Overflow

► Carry

► Parity

► Sign value

**Question No: 4 ( Marks: 1 ) – Please choose one**

The 4-bit 2’s complement representation of “-7” is _____________

► 0111

► 1111

► 1001

► 0110

L-2

**Question No: 5 ( Marks: 1 ) – Please choose one**

AB ABC AC is an example of ________

► Product of sum form

► Sum of product form

► Demorgans law

► Associative law

**Question No: 6 ( Marks: 1 ) – Please choose one**

The diagram given below represents __________

► Demorgans law

► Associative law

► Product of sum form

► Sum of product form

**Question No: 7 ( Marks: 1 ) – Please choose one**

The output of an AND gate is one when _______

► All of the inputs are one

► Any of the input is one

► Any of the input is zero

► All the inputs are zero

**Question No: 8 ( Marks: 1 ) – Please choose one**

The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12

► 16

**Question No: 9 ( Marks: 1 ) – Please choose one**

A BCD to 7-Segment decoder has

► 3 inputs and 7 outputs

► 4 inputs and 7 outputs

► 7 inputs and 3 outputs

► 7 inputs and 4 outputs

**Question No: 10 ( Marks: 1 ) – Please choose one**

Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer.

► 4-input, 8-bit

► 4-input, 16-bit

► 2-input, 8-bit

► 2-input, 4-bit

**Question No: 11 ( Marks: 1 ) – Please choose one**

The PROM

consists of a fixed non-programmable ____________ Gate array configured as a decoder.

► AND

► OR

► NOT

► XOR

**Question No: 12 ( Marks: 1 ) – Please choose one**

In ABEL the variable ‘A’ is treated separately from variable ‘a’

► True

► False

**Question No: 13 ( Marks: 1 ) – Please choose one**

The ABEL notation **equivalent** to Boolean expression A+B is:

► A & B

► A ! B

► A # B

► A $ B

L-21

**Question No: 14 ( Marks: 1 ) – Please choose one**

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input

goes to 0, the latch will be ________.

► SET

► RESET

► Clear

► Invalid

**Question No: 15 ( Marks: 1 ) – Please choose one**

Demultiplexer has

► Single input and single outputs.

► Multiple inputs and multiple outputs.

► Single input and multiple outputs.

► Multiple inputs and single output.

**Question No: 16 ( Marks: 1 ) – Please choose one**

Which one is true:

► Power consumption of TTL is higher than of CMOS

► Power consumption of CMOS is higher than of TTL

► Both TTL and CMOS have same power consumption

► Power consumption of both CMOS and TTL depends on no. of gates in the circuit.

**Question No: 17 ( Marks: 1**** )**

Briefly state the basic principle of **Repeated Division-by-2 **method.

Repeated Division-by-2

Repeated Division-by-2 method allows decimal numbers of any magnitude to be

converted into binary. In this method the Decimal number to be converted into its Binary

equivalent is repeatedly divided by 2. The divisor is selected as 2 because the decimal

number is being converted into Binary a Base-2 Number system. Repeated division

method can be used to convert decimal number into any Number system by repeated

division by the Base-Number. For example, the decimal number can be converted into

the Caveman Number system by repeatedly dividing by 5, the Base number of the

Caveman Number System. The Repeated Division method will be used in latter lectures

to convert decimal into Hexadecimal and Octal Number Systems.

In the Repeated-Division method the Decimal number to be converted is divided

by the Base Number, in this particular case 2. A quotient value and a remainder value is

generated, both values are noted done. The remainder value in all subsequent divisions

would be either a 0 or a 1. The quotient value obtained as a result of division by 2 is

divided again by 2. The new quotient and remainder values are again noted down. In each

step of the repeated division method the remainder values are noted down and the

quotient values are repeatedly divided by the base number. The process of repeated

division stops when the quotient value becomes zero. The remainders that have been

noted in consecutive steps are written out to indicate the Binary equivalent of the Original

Decimal Number.

**Question No: 18 ( Marks: 1**** )**

Briefly state the basic principle of **Repeated Multiplication-by-2 **Method.

Repeated Multiplication-by-2 Method

An alternate to the Sum-of-Weights method used to convert Decimal fractions to

equivalent Binary fractions is the repeated multiplication by 2 method. In this method the

number to be converted is repeatedly multiplied by the Base Number to which the

number is being converted to, in this case 2. A new number having an Integer part and a

Fraction part is generated after each multiplication. The Integer part is noted down and

the fraction part is again multiplied with the Base number 2. The process is repeated until

the fraction term becomes equal to zero.

Repeated Multiplication-by-2 method allows decimal fractions of any magnitude to be

easily converted into binary. The conversion of Decimal fraction 0.625 into Binary

equivalent using the Repeated Multiplication-by-2 method is illustrated in a tabular form.

Table 2.4. Reading the Integer column from bottom to top and placing a decimal point in

the left most position gives 0.101 the binary equivalent of decimal fraction 0.625

**Question No: 19 ( Marks: 2**** )**

**Draw the circuit diagram of a Tri-State buffer****.**

**Question No: 20 ( Marks: 3**** )**

Add -13 and +7 by converting them in binary system your result must be in binary.

**Question No: 21 ( Marks: 5**** )**

Explain “Sum of Weights” method with example for “Octal to Decimal” conversion

1. Sum-of-Weights Method

Sum-of-weights as the name indicates sums the weights of the Binary Digits (bits)

of a Binary Number which is to be represented in Decimal. The Sum-of-Weights method

can be used to convert a Binary number of any magnitude to its equivalent Decimal

representation.

In the Sum-of-Weights method an extended expression is written in terms of the

Binary Base Number 2 and the weights of the Binary number to be converted. The

weights correspond to each of the binary bits which are multiplied by the corresponding

binary value. Binary bits having the value 0 do not contribute any value towards the final

sum expression.

The Binary number 101102 is therefore written in the form of an expression

having weights 20 ,21,22 ,23 AND 24 corresponding to the bits 0, 1, 1, 0 and 1 respectively.

Weights 20AND 23 do not contribute in the final sum as the binary bits corresponding to

these weights have the value 0.

101102 = 1 x 24 0 x 23 1 x 22 1 x 21 0 x 20

= 16 + 0 + 4 + 2 + 0

= 22

**Question No: 22 ( Marks: 10**** )**

Explain the Implementation of an Odd-Parity Generator Circuit i.e by drawing function table, maping it to K-map and then simplifying the expression.

**MIDTERM EXAMINATION**

**CS302- Digital Logic Design**

**Question No: 1 ( Marks: 1 ) – Please choose one**

GAL can be reprogrammed because instead of fuses _______ logic is used in it

► **E****2****CMOS**

► TTL

► CMOS+

► None of the given options

**Question No: 2 ( Marks: 1 ) – Please choose one**

The device shown here is most likely a

► Comparator

**►**** ****Multiplexer**

► Demultiplexer

► Parity generator

**Question No: 3 ( Marks: 1 ) – Please choose one**

If “1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

► 2nd

► 4th

► 14th

► **No output wire will be activated**

**Question No: 4 ( Marks: 1 ) – Please choose one**

Half-Adder Logic circuit contains 2 XOR Gates

► True

► **False**

**Question No: 5 ( Marks: 1 ) – Please choose one**

A particular Full Adder has

**►**** 3 inputs and 2 output**

► 3 inputs and 3 output

► 2 inputs and 3 output

► 2 inputs and 2 output

**Question No: 6 ( Marks: 1 ) – Please choose one**

Sum A BC

CarryOut C(A B) AB

are the Sum and CarryOut expression of

► Half Adder

► **Full Adder**

► 3-bit parralel adder

► MSI adder cicuit

**Question No: 7 ( Marks: 1 ) – Please choose one**

A Karnaugh map is similar to a truth table because it presents all the possible values of

input variables and the resulting output of each value.

► **True**

► False

**Question No: 8 ( Marks: 1 ) – Please choose one**

The output A < B is set to 1 when the input combinations is __________

► A=10, B=01

► A=11, B=01

► A=01, B=01

**►**** A=01, B=10**

**Here output combination should A < B**

**Question No: 9 ( Marks: 1 ) – Please choose one**

The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12

**►**** 16**

**Question No: 10 ( Marks: 1 ) – Please choose one**

Generally, the Power dissipation of _______ devices remains constant throughout their

operation.

**►**** TTL**

► CMOS 3.5 series

► CMOS 5 Series

► Power dissipation of all circuits increases with time.

**Question No: 11 ( Marks: 1 ) – Please choose one**

The decimal “8” is represented as _________ using Gray-Code.

► 0011

**►**** 1100**

► 1000

► 1010

**Question No: 12 ( Marks: 1 ) – Please choose one**

(A+B).(A+C) = ___________

► B+C

**►**** A+BC**

► AB+C

► AC+B

**Question No: 13 ( Marks: 1 ) – Please choose one**

A.(B + C) = A.B + A.C is the expression of _________________

► Demorgan’s Law

► Commutative Law

**►**** ****Distributive Law**

► Associative Law

**Question No: 14 ( Marks: 1 ) – Please choose one**

NOR Gate can be used to perform the operation of AND, OR and NOT Gate

**►**** FALSE**

► TRUE

**Question No: 15 ( Marks: 1 ) – Please choose one**

In ANSI/IEEE Standard 754 “Mantissa” is represented by ___32-bits______ bits

► 8-bits

► 16-bits

**►**** 32****-bits**

► 64-bits

**Question No: 16 ( Marks: 1 ) – Please choose one**

Caveman number system is Base _5_____ number system

► 2

**►**** 5**

► 10

► 16

**Question No: 17 ( Marks: 1 )**

Briefly state the basic principle of **Repeated Multiplication-by-2 **Method.

**Repeated Multiplication-by-2 method allows decimal fractions of any magnitude to**

**be easily converted into binary.**

**Question No: 18 ( Marks: 1 )**

How standard Boolean expressions can be converted into truth table format.

**Standard Boolean expressions can be converted into truth table format ****using binary**

**values for each term in the expression. Standard SOP or POS expressions can**

**also be determined from a truth table.**

**Question No: 19 ( Marks: 2 )**

What will be the out put of the diagram given below

A.B + A.B.C.D

**Question No: 20 ( Marks: 3 )**

**When an Input (source) file is created in ABEL a module is created which has three**

**sections. Name These three sections.**

**Answer:**

The three sections are:

• Boolean Equations

• Truth Tables

• State Diagrams

**Question No: 21 ( Marks: 5 )**

Explain “AND” Gate and some of its uses

**AND gates are used to combine multiple signals, if all the signals are TRUE then the**

**output will also be TRUE. If any of the signals are FALSE, then the output will be**

**false. ANDs aren’t used as much as NAND gates; NAND gates use less components**

**and have the advantage that they be used as an inverter.**

**Question No: 22 ( Marks: 10 )**

**Write down different situations where we need the sequential circuits.**

**Digital circuits that use memory elements for their operation are known as**

**Sequential circuits. Thus Sequential circuits are implemented by combining**

**combinational circuits with memory elements.**

** **

** **

** **

**Question No: 1 ( Marks: 1 ) – Please choose one**

In the binary number “10011” the weight of the most significant digit is ____

► **2****4 ****(2 raise to power 4)**

► 23 (2 raise to power 3)

► 20 (2 raise to power 0)

► 21 (2 raise to power 1)

**Question No: 2 ( Marks: 1 ) – Please choose one**

An S-R latch can be implemented by using _________ gates

► AND, OR

► **NAND, NOR**

► NAND, XOR

► NOT, XOR

**Question No: 3 ( Marks: 1 ) – Please choose one**

A latch has _____ stable states

► One

► **Two**

► Three

► Four

**Question No: 4 ( Marks: 1 ) – Please choose one**

Sequential circuits have storage elements

► **True**

► False

**Question No: 5 ( Marks: 1 ) – Please choose one**

The ABEL symbol for “XOR” operation is

► **$**

► #

► !

► &

**Question No: 6 ( Marks: 1 ) – Please choose one**

A Demultiplexer is not available commercially.

► **True**

► False

**Question No: 7 ( Marks: 1 ) – Please choose one**

Using multiplexer as parallel to serial converter requires ___________ connected to the

multiplexer

► A parallel to serial converter circuit

► **A counter circuit**

► A BCD to Decimal decoder

► A 2-to-8 bit decoder

**Question No: 8 ( Marks: 1 ) – Please choose one**

The device shown here is most likely a

► Comparator

► **Multiplexer**

► Demultiplexer

► Parity generator

**Question No: 9 ( Marks: 1 ) – Please choose one**

The main use of the Multiplexer is to

► **Select data from multiple sources and to route it to a single**

**Destination**

► Select data from Single source and to route it to a multiple Destinations

► Select data from Single source and to route to single destination

► Select data from multiple sources and to route to multiple destinations

**Question No: 10 ( Marks: 1 ) – Please choose one**

A logic circuit with an output consists of ________.

► two AND gates, two OR gates, two inverters

► three AND gates, two OR gates, one inverter

► **two AND gates, one OR gate, two inverters**

► two AND gates, one OR gate

**Question No: 11 ( Marks: 1 ) – Please choose one**

The binary value of 1010 is converted to the product term

► True

► **False**

**Question No: 12 ( Marks: 1 ) – Please choose one**

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► **8**

► 12

► 16

**Question No: 13 ( Marks: 1 ) – Please choose one**

Following is standard POS expression

► **True**

► False

**Question No: 14 ( Marks: 1 ) – Please choose one**

The output of the expression F=A+B+C will be Logic ________ when A=0, B=1,

C=1. the symbol’+’ here represents OR Gate.

► Undefined

► **One**

► Zero

► 10 (binary)

**Question No: 15 ( Marks: 1 ) – Please choose one**

The Extended ASCII Code (American Standard Code for Information Interchange) is a

_____ code

► 2-bit

► **7-bit**

► 8-bit

► 16-bit

**Question No: 16 ( Marks: 1 ) – Please choose one**

The diagram given below represents __________

► Demorgans law

► Associative law

► **Product of sum form**

► Sum of product form

**Question No: 17 ( Marks: 1 )**

**How can a PLD be programmed?**

**PLDs are programmed with the help of computer which runs the programming**

**software. The computer is connected to a programmer socket in which the PLD is**

**inserted for programming. PLDs can also be programmed when they are installed**

**on a circuit board**

**Question No: 18 ( Marks: 1 )**

**How many input and output bits do a Half-Adder contain?**

**The Half-Adder has a 2-bit input and a 2-bit output.**

**Question No: 19 ( Marks: 2 )**

**Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?**

**The circuit of the 1-to-4 Demultiplexer is similar to the 2-to-4 Binary Decoder**

**described earlier figure 16.9. The only difference between the two is the addition**

**of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit**

**figure**

**Question No: 20 ( Marks: 3 )**

**Name the three declarations that are included in “declaration section” of**

**the module that is created ****when an Input (source) file is created in ABEL.**

**Device declaration, pin declarations and set declarations.**

**Question No: 21 ( Marks: 5 )**

**Explain with example how noise affects Operation of a CMOS AND Gate circuit.**

**Two CMOS 5 volt series AND gates are connected together. Figure 7.3 The first**

**AND gate has both its inputs connected to logic high, therefore the output of the**

**gate is guaranteed to be logic high. The logic high voltage output of the first AND**

**gate is assumed to be 4.6 volts well within the valid V****OH ****range of 5-4.4 volts.**

**Assume the same noise signal (as described earlier) is added to the output signal**

**of the first AND gate.**

**Question No: 22 ( Marks: 10 )**

**explain the SOP based implementation ****of the Adjacent 1s Detector Circuit**

**The Adjacent 1s Detector accepts 4-bit inputs. If two adjacent 1s are detected in**

**the**

**input, the output is set to high. The operation of the Adjacent 1s Detector is**

**represented by the**

**function table. Table 13.6. In the function table, for the input combinations 0011,**

**0110, 0111,**

**1011, 1100, 1101, 1110 and 1111 the output function is a 1.**

**Implementing the circuit directly from the function table based on the SOP form**

**requires 8 AND gates for the 8 product terms (minterms) with an 8-input OR gate.**

**Figure 13.3.**

**The total gate count is**

**• One 8 input OR gate**

**• Eight 4 input AND gates**

**• Ten NOT gates**

**The expression can be simplified using a Karnaugh map, figure 13.4, and then the**

**simplified expression can be implemented to reduce the gate count. The**

**simplified expression**

**is****AB + CD +BC ****. The circuit implemented using the expression ****AB + CD +BC**

**has reduced**

**to 3 input OR gate and 2 input AND gates.**

**The simplified Adjacent 1s Detector circuit uses only four gates reducing the cost,**

**the**

**size of the circuit and the power requirement. The propagation delay of the circuit**

**is of the order of two gates**

.